Pro-Form ZE5 Spécifications Page 78
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- Table des matières
- MARQUE LIVRES
- Zylogic ZE5 Configurable 1
- System-on-Chip Platform 1
- Overview 3
- Triscend 4
- Configurable 4
- System-on-Chip 4
- DMA Controller 6
- 76543210 10
- ADRM1 ADRM0 11
- Data Write 19
- Data Read 20
- TE505 (2x2) 22
- TE512 (3x3) 22
- TE520 (4x4) 22
- TE532 (5x5) 22
- TE502 (2x1) 22
- 27 www.zylogic.com.cn 27
- Dual-Port 29
- Mode D ClkEna Clock Q 32
- Memory Interface Unit 34
- SETUP STROBE HOLD 35
- SETUP STROBE 36
- Address Mappers 38
- Mask = 2 40
- BLOCK_SIZE 40
- A15 A14 A13 A12 A11 A10 A9 A8 42
- Configurable System-on-Chip 47
- System Initialization 48
- Triscend E5 49
- External Parallel Memory 49
- (optional) 50
- Upper Address 50
- Application Dependent 50
- (Slave Mode) 51
- External Controller or 51
- Master E5 CSoC 51
- Clock input signal 54
- (Reads = 0) 58
- EA - ET2 ES ET1 EX1 ET0 EX0 60
- - - PT2 PS PT1 PX1 PT0 PX0 61
- - - - - - - - DCEN 62
- CY AC F0 RS1 RS0 OV F1 P 62
- Instruction Set 64
- Interrupts 66
- (highest) 67
- (lowest) 67
- Reset Conditions 69
- Power Management 71
- - -PIOXTALOSCGBUF 72
- - ------PORCT 72
- Glossary 74
- Life Support Policy 74
- Revision List 74
- 75 www.zylogic.com.cn 75
- Pin Description 76
- Pinout Diagrams and Tables 79
- TE502S08L 80
- TE505S16L 80
- TE512S32L 80
- Top View 83
- TE505S16Q 84
- TE512S32Q 84
- TE520S40Q 84
- TE532S64Q 84
- TE520S40B 89
- 91 www.zylogic.com.cn 91
- Bottom View 93
- 35 pF12 mA 96
- [1] Max Max 98
- External 99
- Byte-wide 99
- C1 C2 C3 C4 C4 C1 100
- www.zylogic.com.cn 101
- Start Here 102
- Bus Clock 104
- Flip-flop 108
- BCLK/XTAL 115
- BusClock 115
- Output Voltage (V) 118
- Output Current (mA) 118
- TE5 20 S 40 - 40 Q C 119
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